1. Field of the Invention
The invention relates to computer clocking systems, and more particularly, to methods of and devices for preventing the free running frequency in phase-locked loops from exceeding the allowable input frequency for flip-flops in the phase-locked loops.
2. Description of the Related Art
In efforts to realize greater computing power, microprocessor developers have continuously pushed the clock speeds ever higher. As few as ten years ago, microprocessor clock frequencies of 16 MHz were rare. Today, one sees microprocessors running at frequencies of 66 MHz and even higher.
With these higher clock frequencies have come concurrent problems. Distribution of a 66 MHz clock to the various components of a digital computer system can present difficulties associated with electromagnetic interference (EMI), clock skew, and reflections of the higher harmonics of the system clock signal. Transmission of high frequency clock signals across connectors to companion boards exacerbates these problems.
Developers have sought creative solutions to these problems. One approach has been to rely on a lower frequency system clock, and then generate, on the microprocessor or peripheral chip itself, a higher frequency clock signal from that lower frequency system clock. A number of current microprocessors and peripheral chips implement such a technique-for example, the 80486DX2 by Intel Corporation. This technique has the advantage of increasing a chip's internal processing rate without requiring a corresponding increase in system clock frequency, thus avoiding the problems associated with those higher clock rates.
To generate these higher frequency internal clock signals, these chips typically use a phase-locked loop (PLL) configured as a frequency multiplier. A block diagram of such a frequency multiplier circuit is shown in FIG. 1. As is shown, a phase detector (or phase comparator) drives, through a low-pass filter, a voltage controlled oscillator (VCO). The output of that voltage controlled oscillator, which becomes the output signal, is then divided by the desired multiplication factor. The phase detector then compares that divided reference signal with the input signal. This feedback arrangement compensates for shifts in the phase and frequency of the input signal by a level shift to the voltage controlled oscillator, and the output signal is thus synchronized to the input signal. Examples of PLLs that can be configured as frequency multipliers include the CD4046A by RCA Corporation and the 74LS297.
The phase detector has two main purposes. First, it forces the voltage controlled oscillator to shift frequencies when the reference signal and the input signal are of different frequencies. Second, using feedback it forces slight corrections to the voltage controlled oscillator output when the reference and input signals are of the same frequency but are slightly out of phase. Both of these functions are accomplished by adjusting the frequency of the voltage controlled oscillator; it is simply a difference of the magnitude of the adjustment.
Before an input frequency is provided to the phase detector shown in FIG. 1, the voltage controlled oscillator runs at a certain "free running" frequency. This can be higher or lower than the subsequent locked-in frequency, but is typically higher in PLLs as used in microcomputers. The frequency of the output signal of the voltage controlled oscillator is proportional to the voltage across the filtering capacitor. When "free running," the filtering capacitor will be at its maximum voltage, which in turn causes the voltage controlled oscillator to run at its maximum frequency.
To provide an output frequency which is a multiple of the input frequency, a divider stage divides the voltage controlled oscillator output signal before providing it to the phase detector. The divider stage is typically constructed from a flip-flop or stages of flip-flops. To divide by 2, a single flip-flop halves the voltage controlled oscillator output; to divide by 4, two flip-flops are staged. Of course, frequency dividers are well-known in the art, and one can divide by factors other than multiples of 2 using appropriate combinations of flip-flops or counters.
As can be seen in FIG. 1, the divider stage is driven by the output of the voltage controlled oscillator. The flip-flops and counters in the divider stage, however, typically have a maximum input frequency at which they can reliably track. This necessitates a trade off between speed and cost; the faster the flip-flops, and thus the higher the maximum speed of the PLL, the greater the cost. A maximum free running frequency of 300 MHz is easily achievable for the voltage controlled oscillator stage, but flip-flops for the divider stage capable of running at 300 MHz can be expensive to construct in integrated circuits. The same problem exists in a non-multiplying PLL. The phase-detector in such a PLL is fed directly from the voltage controlled oscillator, and that signal may exceed the capabilities of the input buffers of the phase detector.
Therefore, it is desirable to construct PLLs using lower speed flip-flops in the divider stage. Similarly, it is also desirable to construct PLLs using phase detectors with lower speed input buffers. However, problems may develop in those cases as the free running frequency of the voltage controlled oscillator may cause indeterminate states or erratic operation of the flip-flops and phase detector. This problem could then lead to recurring errors so that the PLL is never able to lock in on the desired frequency, even after an input signal is provided. Therefore, it is desirable to be able to use the lower frequency flip-flops and phase detectors and yet not have this lock failure problem.